Enum CpuState 

pub enum CpuState {
    FetchOpcode,
    FetchOperandLo,
    FetchOperandHi,
    ResolveAddress,
    ReadData,
    WriteData,
    RmwRead,
    RmwDummyWrite,
    RmwWrite,
    Execute,
    FetchIndirectLo,
    FetchIndirectHi,
    AddIndex,
    PushHi,
    PushLo,
    PushStatus,
    PopLo,
    PopHi,
    PopStatus,
    InternalCycle,
    BranchTaken,
    BranchPageCross,
    InterruptPushPcHi,
    InterruptPushPcLo,
    InterruptPushStatus,
    InterruptFetchVectorLo,
    InterruptFetchVectorHi,
}

CPU execution state for cycle-by-cycle execution.

Each state represents one CPU cycle with one bus access. The state machine transitions through these states to execute instructions with perfect cycle accuracy.

Variants

FetchOpcode

Fetch opcode from PC (cycle 1 of every instruction)

FetchOperandLo

Fetch low byte of operand

FetchOperandHi

Fetch high byte of operand

ResolveAddress

Resolve effective address (internal operation or dummy read) Used for indexed addressing modes with page crossing

ReadData

Read data from effective address

WriteData

Write data to effective address

RmwRead

Read-Modify-Write: Read phase

RmwDummyWrite

Read-Modify-Write: Dummy write old value (hardware behavior)

RmwWrite

Read-Modify-Write: Write new value

Execute

Execute internal operation (no bus access, register-only)

FetchIndirectLo

Fetch indirect address low byte (for indirect addressing)

FetchIndirectHi

Fetch indirect address high byte (for indirect addressing)

AddIndex

Add index to indirect address (indexed indirect)

PushHi

Push high byte to stack

PushLo

Push low byte to stack

PushStatus

Push status to stack

PopLo

Pop low byte from stack (with internal cycle)

PopHi

Pop high byte from stack

PopStatus

Pop status from stack

InternalCycle

Internal cycle (dummy stack read)

BranchTaken

Branch taken - calculate new PC

BranchPageCross

Branch page cross - extra cycle for crossing page

InterruptPushPcHi

Interrupt: Push PC high

InterruptPushPcLo

Interrupt: Push PC low

InterruptPushStatus

Interrupt: Push status

InterruptFetchVectorLo

Interrupt: Fetch vector low

InterruptFetchVectorHi

Interrupt: Fetch vector high

Implementations

impl CpuState

pub const fn is_read(&self) -> bool

Returns true if this state requires a bus read.

pub const fn is_write(&self) -> bool

Returns true if this state requires a bus write.

pub const fn is_internal(&self) -> bool

Returns true if this is an internal operation (no bus access visible).

Trait Implementations

impl Clone for CpuState

fn clone(&self) -> CpuState

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for CpuState

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for CpuState

fn default() -> CpuState

Returns the “default value” for a type.

impl PartialEq for CpuState

fn eq(&self, other: &CpuState) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for CpuState

impl Eq for CpuState

impl StructuralPartialEq for CpuState