Crate rustynes_cpu 

RustyNES CPU - Cycle-accurate 6502 emulation

This crate provides a cycle-accurate implementation of the MOS 6502 CPU as used in the Nintendo Entertainment System (NES). It includes:

• All 256 opcodes (151 official + 105 unofficial)
• Cycle-accurate timing
• Complete interrupt handling (NMI, IRQ, BRK, RESET)
• All addressing modes
• Zero unsafe code

Example

use rustynes_cpu::{Cpu, Bus};

// Implement the Bus trait for your system
struct MyBus {
    memory: [u8; 0x10000],
}

impl Bus for MyBus {
    fn read(&mut self, addr: u16) -> u8 {
        self.memory[addr as usize]
    }

    fn write(&mut self, addr: u16, value: u8) {
        self.memory[addr as usize] = value;
    }
}

fn main() {
    let mut cpu = Cpu::new();
    let mut bus = MyBus { memory: [0; 0x10000] };

    // Set RESET vector to 0x8000
    bus.memory[0xFFFC] = 0x00;
    bus.memory[0xFFFD] = 0x80;

    // Reset CPU
    cpu.reset(&mut bus);

    // Execute instructions
    loop {
        let cycles = cpu.step(&mut bus);
        // Execute cycles CPU cycles worth of other system components
    }
}

Accuracy

This implementation is designed to pass:

• nestest.nes golden log
• blargg’s cpu_timing_test6
• All TASVideos accuracy tests

Architecture

• Modular Design: CPU, PPU, APU, and mappers are separate crates
• Strong Typing: Newtype pattern for addresses and flags
• Safe Code: Zero unsafe blocks (except for FFI in other crates)
• Trait-Based: Bus trait allows flexible memory systems

Feature Flags

Currently no optional features. All functionality is included by default.

Re-exports

pub use ines::INesHeader;

pub use ines::INesRom;

pub use trace::CpuTracer;

Modules

ines

iNES ROM format loader.

state

CPU execution state machine for cycle-accurate emulation.

trace

CPU trace logging for nestest.log-compatible output.

Structs

Cpu

NES 6502 CPU

StatusFlags

CPU Status Register Flags (P register)

Enums

AddressingMode

CPU Addressing Modes

Constants

OPCODE_TABLE

Complete 256-entry opcode lookup table.

Traits

Bus

Memory bus interface

CpuBus

Cycle-accurate bus interface for sub-cycle PPU/APU synchronization