Expand description
Architecture-independent memory barrier abstractions.
Centralizes memory barrier/fence operations so that non-arch code does not
need scattered #[cfg(target_arch)] blocks with inline assembly.
§Barrier types
memory_fence– full read/write fence (strongest).data_sync_barrier– data synchronization barrier with instruction synchronization on AArch64; equivalent to a full fence on other architectures.instruction_sync_barrier– instruction stream synchronization (AArch64 ISB, RISC-V FENCE.I, x86_64 no-op because of strong ordering).
Functions§
- data_
sync_ barrier - Data synchronization barrier with instruction synchronization.
- instruction_
sync_ barrier - Instruction synchronization barrier.
- memory_
fence - Full memory fence – all reads and writes issued before this barrier are globally visible before any reads or writes issued after it.