pub fn instruction_sync_barrier()Expand description
Instruction synchronization barrier.
Ensures that all preceding instructions have completed and the instruction pipeline is flushed before subsequent instructions execute. This is primarily needed on AArch64 and RISC-V after modifying code pages or after a data barrier that affects instruction fetch.
- x86_64: no-op – x86_64’s strong ordering model and unified cache make an explicit instruction barrier unnecessary in most scenarios.
- AArch64:
isb– Instruction Synchronization Barrier. - RISC-V:
fence.i– Instruction fence.