pub fn data_sync_barrier()Expand description
Data synchronization barrier with instruction synchronization.
On AArch64 this issues dsb sy followed by isb, which is the standard
pattern used when a data store must be visible before instruction fetch
proceeds (e.g., writing to a pointer that will be dereferenced
immediately after).
On other architectures this is equivalent to memory_fence because
their memory models already guarantee the necessary ordering.
- x86_64:
core::sync::atomic::fence(SeqCst). - AArch64:
dsb sy+isb. - RISC-V:
fence rw, rw.