pub struct StepResult {
pub dma: Option<Dma>,
pub interrupt_change: Option<bool>,
pub dp_write: Option<(u8, u32)>,
}Expand description
What one scalar step asked the rest of the machine to do.
The RSP cannot reach RDRAM or the MI itself — it does not own them — so it
reports rather than acts, and rustyn64-core::Bus carries it out. This is
the same shape the PI engine uses, and it is what lets the RSP be stepped in
isolation.
Fields§
§dma: Option<Dma>A transfer an MTC0 to a length register started.
interrupt_change: Option<bool>A change to the MI’s SP interrupt line: Some(true) raises it,
Some(false) acknowledges it, None leaves it alone.
Three states rather than two, because the RSP acknowledges its own
interrupt by writing CLR_INTR through MTC0 — with a plain bool,
“clear the line” and “this step said nothing about the line” are the
same value, and the acknowledgment is silently dropped.
dp_write: Option<(u8, u32)>An MTC0 to a DP command register (c8–c15), reported as a
DPC word offset 0–7 (0=DP_START, 1=DP_END,
2=DP_CURRENT, 3=DP_STATUS, 4–7 the clock/busy counters) and
the value.
Those COP0 registers are the RDP’s command registers, but the RSP
crate may not depend on rustyn64-rdp (the crate graph forbids that
chip→chip edge — docs/architecture.md). So the write is reported here
and rustyn64-core::Bus forwards it to Rdp::dpc_write, exactly as
dma and interrupt_change are carried out by the owner.
Trait Implementations§
Source§impl Clone for StepResult
impl Clone for StepResult
Source§fn clone(&self) -> StepResult
fn clone(&self) -> StepResult
1.0.0 · Source§fn clone_from(&mut self, source: &Self)
fn clone_from(&mut self, source: &Self)
source. Read more