Module su 

The scalar unit — the RSP’s MIPS-like integer core (T-21-004).

Close enough to a 32-bit R4000 that standard MIPS documentation covers most of it, so what this module records is the differences (N64brew RSP CPU Core §Scalar unit):

• No multiply/divide unit. MULT, MULTU, DIV, DIVU, MFHI, MFLO, MTHI, MTLO do not exist, and neither does HI/LO.
• No 64-bit anything. The registers are 32 bits, so every D* opcode is absent, as are LD/SD/LDL/SDL.
• No misaligned-access opcodes, because none are needed: LW and SW work at any address. LWL/LWR/SWL/SWR are absent.
• No traps or exceptions at all — no interrupts, no SYSCALL, no TGE family. BREAK exists and halts the core instead of raising anything.
• No likely branches (BEQL, BLEZL, …).

The two rules that catch a MIPS core reused wholesale

The PC is 12 bits and wraps. Every high bit of a branch or jump target is discarded, and running off the end of IMEM at 0xFFC continues at 0x000 rather than faulting. n64-systemtest’s RSP Wrap around places two nops at 0xFF8 and a BREAK at 0x000, runs from 0xFF8, and expects to stop at 0x4.

Misaligned data accesses are correct, not faults. A LW at 0x001 returns the four bytes at 0x1..=0x4; the address is masked to 12 bits and each byte wraps inside DMEM independently, so a word read at 0xFFE takes two bytes from the end and two from the start. On the VR4300 the same access is an AddressError, which makes this the single easiest place to get the RSP wrong by reusing CPU code.

Structs

StepResult

What one scalar step asked the rest of the machine to do.