pub struct SpRegs { /* private fields */ }Expand description
The SP interface registers.
Implementations§
Source§impl SpRegs
impl SpRegs
Sourcepub const fn new() -> Self
pub const fn new() -> Self
Power-on state: halted, semaphore free.
The RSP comes out of reset halted and idles until the CPU clears the bit;
n64-systemtest’s StartupTest reads SP_STATUS expecting exactly 0x1.
Sourcepub const fn broke(&self) -> bool
pub const fn broke(&self) -> bool
Has a BREAK executed since BROKE was last cleared? Distinct from
Self::halted: a SET_HALT write halts without setting BROKE, so a
consumer that wants “the microcode reached a break” must check this.
Sourcepub const fn set_broke(&mut self, broke: bool)
pub const fn set_broke(&mut self, broke: bool)
Latch BROKE. Set by a BREAK and cleared only by a CLR_BROKE write:
it remembers that a break happened, independently of run state.
Sourcepub const fn set_halted(&mut self, halted: bool)
pub const fn set_halted(&mut self, halted: bool)
Halt or release the RSP from within the chip (a BREAK, or single-step).
Sourcepub const fn read(&mut self, index: u32) -> u32
pub const fn read(&mut self, index: u32) -> u32
Read a register by index. mi_sp is not touched here — see Self::write.
Sourcepub const fn write(&mut self, index: u32, val: u32) -> Option<Dma>
pub const fn write(&mut self, index: u32, val: u32) -> Option<Dma>
Write a register by index.
Returns a Dma when the write started one — the Bus performs it, for
the reason given on that type.
The SP interrupt line is not updated here. SP_STATUS can both raise
and acknowledge it, so the caller reads Self::interrupt_change
afterwards; returning it through the same channel as a DMA would conflate
two independent effects of one write.
Sourcepub const fn interrupt_change(val: u32) -> Option<bool>
pub const fn interrupt_change(val: u32) -> Option<bool>
What a SP_STATUS write did to the MI’s SP interrupt line.
Some(true) raises it, Some(false) acknowledges it, None leaves it
alone. Separate from Self::write because the line lives in the MI,
not here, and because one write can start a DMA and touch the line.
Sourcepub const fn complete_dma(&mut self, sp_addr: u32, ram_addr: u32)
pub const fn complete_dma(&mut self, sp_addr: u32, ram_addr: u32)
Record where a completed transfer left the address and length registers.
Hardware leaves the pointers past the data it moved, and the length
field at 0xFF8 — it is decremented by 8 per word and ends at -8.
COUNT resets to 0 and SKIP is preserved, which is why only the low
field is rewritten here.