Module sp 

The SP interface register file (T-21-002).

Eight registers at 0x0404_0000 plus SP_PC at 0x0408_0000, memory-mapped into the VR4300’s address space and simultaneously exposed to the RSP itself as COP0 registers c0–c7. There is one set of physical registers behind both views (N64brew RSP Interface §RSP Internal Registers), which is why this module holds them rather than either side owning a copy.

Why the write layout differs from the read layout

SP_STATUS reads as a flag word and writes as a list of set/clear commands — two bits per flag. That is not an encoding quirk to normalize away: it exists so either processor can change one flag with a single store, without the read-modify-write that would race the other. Collapsing the two layouts into one would reintroduce exactly the race the hardware design removes.

The corollary is the rule that catches naive implementations: writing a flag’s set and clear bits together leaves it unchanged. n64-systemtest checks this for every flag it can reach.

Modules

reg

Register indices, shared by the CPU’s 0x0404_00xx window and the RSP’s COP0 c0–c7.

Structs

Dma

A programmed DMA, latched from the address and length registers.

SpRegs

The SP interface registers.

Constants

STATUS_BROKE

SP_STATUS.BROKE — a BREAK has executed since this was last cleared.

STATUS_DMA_BUSY

SP_STATUS.DMA_BUSY — a transfer is in progress.

STATUS_DMA_FULL

SP_STATUS.DMA_FULL — a second transfer is queued behind the current one.

STATUS_HALTED

SP_STATUS.HALTED — the RSP is paused and fetches nothing.

STATUS_INTBREAK

SP_STATUS.INTBREAK — raise the MI interrupt when BREAK executes.

STATUS_IO_BUSY

SP_STATUS.IO_BUSY.

STATUS_SIG0

SP_STATUS.SIG0 — the first of eight software-defined signal bits.

STATUS_SSTEP

SP_STATUS.SSTEP — single-step mode.