pub fn convert(bits: u64, from: Format, to: Format, mode: Rounding) -> RoundedExpand description
Convert between formats — CVT.S.D narrowing, CVT.D.S widening.
§Why a conversion belongs here and not in fpu
Narrowing is an arithmetic operation. CVT.S.D has to round a 53-bit
significand into 24, so it can be inexact, can overflow to infinity, and can
underflow into the subnormal range — and each of those depends on
FCSR.RM. A v as f32 cast reports none of it and rounds to nearest only,
which is where accuracy ledger C-11 found this operation still sitting after
the arithmetic had been fixed.
Widening cannot lose anything, but goes through the same path so there is one conversion rather than two that can disagree.
§NaN handling
A NaN operand yields the target format’s default NaN, flagged Invalid when the operand signals. The VR4300’s other NaN class — significand MSB clear, quiet by its convention (ledger C-12) — raises unimplemented operation instead and is rejected by the caller before reaching here, so it is deliberately not a case below.