pub struct RcpRegs {
pub mi_intr: MiInterrupt,
pub mi_mask: MiInterrupt,
pub mi_mode: u32,
pub ri: [u32; 8],
}Expand description
The RCP interface register state.
The SP / DP / VI / AI / PI / SI / RI / MI register blocks the CPU memory-maps
in $0400_0000..$04FF_FFFF. Skeleton: each is a placeholder for its real
register set (a roadmap phase).
Fields§
§mi_intr: MiInterruptMI — MIPS interface (interrupt lines + mask + RCP version).
mi_mask: MiInterruptMI interrupt mask (a line drives IP2 only when masked-in).
mi_mode: u32MI_MODE’s storage bits (the repeat count and flags).
ri: [u32; 8]The RI (RDRAM controller) register file, 0x0470_0000..0x0470_0020:
RI_MODE, RI_CONFIG, RI_CURRENT_LOAD, RI_SELECT, RI_REFRESH,
RI_LATENCY, RI_ERROR, RI_BANK_STATUS (N64brew RDRAM Interface
§Registers).
Plain storage — writes stick and reads return them. That is enough for the
one thing that actually depends on it today: the cartridge’s IPL3 reads
RI_SELECT and branches on whether RDRAM has already been brought up
(ledger R-18). The documented read oddities are deliberately NOT modeled
(see R-22): RI_CURRENT_LOAD is write-only on hardware and its read
returns a collection of bits from other registers, and RI_ERROR /
RI_BANK_STATUS reflect controller state rather than the last write.
Nothing exercises those yet and there is no oracle for them — the suite has
no RI group — so they stay honest storage rather than invented behavior.