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Module bus

Module bus 

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The Bus owns everything mutable.

RDRAM (main work RAM), the RSP, the RDP, the AI (audio), the cart (→ PI), the controllers (→ SI), and the RCP interface register blocks (SP / DP / VI / AI / PI / SI / RI / MI). The CPU borrows &mut Bus during tick(). The RDP and AI see narrower bus traits (rustyn64_rdp::VideoBus, rustyn64_audio::AudioBus) which the Bus implements. See docs/architecture.md (the load-bearing facts).

Per the TetaNES postmortem (carried over from RustyNES): one owner for all mutable state avoids the “CPU holds the RSP/RDP, but they also need the CPU’s memory bus” borrow-checker fight. Each chip sees only the smaller trait it actually needs.

Structs§

Bus
Everything mutable lives here — the single owner.
MiInterrupt
The RCP MIPS-interface (MI) interrupt lines.
RcpRegs
The RCP interface register state.

Constants§

RDRAM_PAGE
Granularity of the RDRAM dirty-page map, in bytes.
RDRAM_SIZE
Base RDRAM size: 4 MiB (8 MiB with the Expansion Pak installed).