Struct Pif

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pub struct Pif { /* private fields */ }

Expand description

The PIF: its 64-byte RAM plus the per-channel accessory-change latch.

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impl Pif

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pub const fn new() -> Self

Power-on PIF (RAM cleared, no pak, no boot ROM).

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pub const fn set_controllers_connected(&mut self, connected: [bool; 4])

Set which joybus controller ports (0-3) have a device plugged in.

Defaults to port 1 only. A frontend offering 2-4 player support sets the extra ports here; without it every additional port reports “no device” and osContInit sees a single pad, which is correct for the default machine but wrong for a multiplayer session.

Channel 4 (the cartridge/EEPROM bus) is not a controller port and is not addressed by this — its presence follows the installed save device.

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pub const fn controllers_connected(&self) -> [bool; 4]

Which controller ports currently report a device.

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pub fn load_boot_rom(&mut self, bytes: &[u8])

Install the PIF boot ROM (IPL1/IPL2) for the real-PIF boot path. Accepts the raw dump; only the first PIF_ROM_LEN bytes (the ROM window) are kept — a longer dump that also carries the 64-byte RAM tail is truncated. Too-short input leaves the ROM absent (the real-PIF boot then cannot run).

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pub const fn has_boot_rom(&self) -> bool

Is a real PIF boot ROM installed?

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pub fn boot_rom_read(&self, off: usize) -> u8

Read a byte of the PIF boot ROM (0x1FC0_0000 + off, off < PIF_ROM_LEN). Reads back 0 when no ROM is installed (HLE), once IPL2 has locked the ROM (0x10 command), or off is out of range — the same value the unmapped PIF-ROM window returned before this path existed.

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pub const fn reset_boot(&mut self)

Warm-reset the transient real-PIF boot state so a reset can re-run IPL1→IPL2 (PIF-NUS.md §Console Reset: the PIF unlocks the PIF ROM on the reset NMI). Clears the ROM lockout and the latched checksum; keeps the installed boot ROM and the registered CIC checksum — the cartridge is still inserted, so the CIC would re-hand-off the same values.

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pub const fn set_boot_checksum(&mut self, checksum: [u8; 6])

Register the CIC’s 6-byte IPL2 checksum for the real-PIF boot verify.

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pub fn boot_command(&mut self) -> bool

Process a reset-mode PIF command-byte write during the real-PIF boot, returning true if the checksum verify FAILED and the caller must NMI-halt the CPU (PIF-NUS.md §Console startup 8.7). No-op (returns false) unless a boot ROM is installed, so the run-mode joybus path is unaffected.

The command bits (PIF-NUS.md reset-mode table, cross-checked against the SM5 firmware and the IPL2 stores at bfc006xx):

0x10 ROM lockout — remove the PIF-ROM from the bus (reads 0 after).
0x20 acquire checksum — latch the 6 bytes IPL2 wrote to 0x32-0x37, zero them in PIF RAM, and set bit 0x80 to acknowledge (IPL2 spins on it).
0x40 run checksum — compare the latched value against the CIC’s; a mismatch halts the CPU, a match lets IPL2’s unconditional jump reach IPL3.

Each handled bit is cleared after processing; bit 0x80 is PIF-owned.

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pub const fn set_pak_present(&mut self, channel: usize, present: bool)

Report a Controller Pak on port channel (0–3) — the info status byte then advertises it and 0x02/0x03 route to the cart save.

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pub const fn ram(&self) -> &[u8; 64]

The 64-byte PIF RAM (for the SI DMA to copy to/from RDRAM).

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pub fn read(&self, off: usize) -> u8

A byte of PIF RAM (CPU direct read at 0x1FC0_07C0 + off).

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pub const fn write(&mut self, off: usize, val: u8)

Write a byte of PIF RAM (CPU direct write / SI DMA).

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pub fn load(&mut self, bytes: &[u8; 64])

Replace the whole PIF RAM (an SI 64-byte DMA write from RDRAM).

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pub fn execute(&mut self, controllers: &[u32; 4], save: &mut SaveDevice)

Execute the joybus frame if the command byte requests it (bit 0), filling each handshake’s reply region. Called on an SI read (the point at which the PIF runs the handshakes), then the caller DMAs PIF RAM out.