Module pif 

The PIF RAM + the SI joybus frame executor (controllers, EEPROM, Pak). The PIF RAM (64 bytes) + the joybus frame executor.

The CPU fills PIF RAM with a joybus frame — a sequence of up to five per-channel handshakes TX RX tt[..] rr[..] (channels 0–3 = controller ports, channel 4 = the cartridge bus / EEPROM) — sets the command byte (0x3F) bit 0, and triggers an SI DMA. On the SI read the PIF executes the handshakes and writes the replies back into the rr[..] regions (n64brew_wiki/markdown/PIF-NUS.md, Joybus protocol.md).

We model the common commands: 0x00/0xFF info, 0x01 controller state, 0x02/0x03 Controller-Pak accessory access, and 0x04/0x05 EEPROM. Controller state comes from the Bus’s four packed port words; the accessory and EEPROM backing is the cart’s crate::save::SaveDevice.

Structs

Pif

The PIF: its 64-byte RAM plus the per-channel accessory-change latch.

Constants

PIF_RAM_LEN

PIF RAM size (bytes). The last byte (0x3F) is the command bitmask.

PIF_ROM_LEN

PIF boot ROM size (bytes) — IPL1 + IPL2.

Functions

data_crc

The joybus accessory data CRC8 (seed 0x00, polynomial 0x85 — Joybus protocol.md §Data CRC).