Struct VirtualLapic 

pub struct VirtualLapic {

    pub id: u32,
    pub tpr: u32,
    pub svr: u32,
    pub isr: [u32; 8],
    pub irr: [u32; 8],
    pub tmr: [u32; 8],
    pub lvt_timer: LvtEntry,
    pub lvt_thermal: LvtEntry,
    pub lvt_perfmon: LvtEntry,
    pub lvt_lint0: LvtEntry,
    pub lvt_lint1: LvtEntry,
    pub lvt_error: LvtEntry,
    pub timer_initial_count: u32,
    pub timer_current_count: u32,
    pub timer_divide_config: u32,
    pub tsc_deadline: u64,
    pub esr: u32,
    pub icr_low: u32,
    pub icr_high: u32,
    pub ldr: u32,
    pub dfr: u32,
    pub enabled: bool,
}

Virtual LAPIC state

Fields

id: u32

LAPIC ID

tpr: u32

Task Priority Register

svr: u32

Spurious Interrupt Vector Register

isr: [u32; 8]

In-Service Register (256 bits = 8 x u32)

irr: [u32; 8]

Interrupt Request Register (256 bits = 8 x u32)

tmr: [u32; 8]

Trigger Mode Register (256 bits = 8 x u32)

lvt_timer: LvtEntry

LVT Timer entry

lvt_thermal: LvtEntry

LVT Thermal entry

lvt_perfmon: LvtEntry

LVT Performance Monitor entry

lvt_lint0: LvtEntry

LVT LINT0 entry

lvt_lint1: LvtEntry

LVT LINT1 entry

lvt_error: LvtEntry

LVT Error entry

timer_initial_count: u32

Timer initial count

timer_current_count: u32

Timer current count (decrements)

timer_divide_config: u32

Timer divide configuration

tsc_deadline: u64

TSC deadline value

esr: u32

Error status register

icr_low: u32

Interrupt Command Register (low 32 bits)

icr_high: u32

Interrupt Command Register (high 32 bits)

ldr: u32

Logical Destination Register

dfr: u32

Destination Format Register

enabled: bool

Whether the LAPIC is enabled (via SVR bit 8)

Implementations

impl VirtualLapic

pub fn new(id: u32) -> Self

pub fn read_register(&self, offset: u32) -> u32

Handle MMIO read from LAPIC register space

pub fn write_register(&mut self, offset: u32, value: u32)

Handle MMIO write to LAPIC register space

pub fn accept_interrupt(&mut self, vector: u8)

Accept an interrupt: set IRR bit

pub fn deliver_pending_interrupt(&mut self) -> Option<u8>

Try to deliver next pending interrupt (IRR -> ISR)

pub fn tick_timer(&mut self, ticks: u32) -> bool

Tick the LAPIC timer (called periodically by hypervisor) Returns true if timer interrupt should fire

pub fn timer_divide_value(&self) -> u32

Get the timer divide value from config register

pub fn extract_ipi(&self) -> IpiMessage

Extract IPI delivery info from ICR

pub fn is_enabled(&self) -> bool

Check if the LAPIC is software-enabled

pub fn base_address() -> u64

Get the LAPIC base address

pub fn region_size() -> u64

Get the LAPIC region size