Module cache_aligned 

Cache Line Alignment Utilities

Provides types and constants for eliminating false sharing in concurrent data structures. False sharing occurs when independent variables share a cache line, causing cache invalidation ping-pong between CPU cores on writes.

Modern x86_64 (Intel/AMD) and AArch64 (Cortex-A72) use 64-byte cache lines. RISC-V implementations also commonly use 64 bytes.

Structs

CacheAligned

Cache-line-aligned wrapper type for eliminating false sharing.

Constants

CACHE_LINE_SIZE

Cache line size in bytes for the target architecture.