pub const CACHE_LINE_SIZE: usize = 64;Expand description
Cache line size in bytes for the target architecture.
Intel/AMD x86_64: 64 bytes (since Pentium 4). ARM Cortex-A72: 64 bytes (L1D and L2). Common RISC-V implementations: 64 bytes.
pub const CACHE_LINE_SIZE: usize = 64;Cache line size in bytes for the target architecture.
Intel/AMD x86_64: 64 bytes (since Pentium 4). ARM Cortex-A72: 64 bytes (L1D and L2). Common RISC-V implementations: 64 bytes.