Enum Cpu2A03Revision 

pub enum Cpu2A03Revision {
    Rp2A03G,
    Rp2A03H,
}

Ricoh 2A03 CPU/APU die revision, selecting the hardware-revision difference in the DMA unit’s “unexpected DMA” extra halt-read (v2.1.7 “Hardware Revisions & DMA Frontier”).

The frontier — read this before trusting the non-default arm

The 2A03 shipped in several mask revisions. nesdev (DMA) documents that when a DMC DMA halt is requested on a CPU cycle where an OAM ($4014) DMA is also halting — the “double-halt” overlap — some silicon performs an extra re-read of the parked 6502 address bus before the transfer resumes (the “unexpected DMA” read), and this differs by die revision.

No public reference emulator models this die-revision difference, and no public test ROM verifies it. A survey of Mesen2, ares, BizHawk, TriCNES, fceux, nestopia, GeraNES, and higan (v2.1.7, see ADR 0033) found that none branch DMA cycle behavior on 2A03 die stepping — the only revision-like switch any of them models is the orthogonal console-type distinction (Mesen2 isNesBehavior: NES-001/AV-Famicom clock a controller only on the first DMA idle read, original Famicom on every one), which is a different axis and is already reflected in this core’s default register-readout model. The die-revision extra-read is therefore a genuine open frontier: this enum provides the config surface for it and a conservative, deterministic model, but the Rp2A03H arm’s direction is an unverified hypothesis, not an oracle-proven behavior.

Contract

• Default = Rp2A03G is byte-identical to the core as it shipped before v2.1.7 (AccuracyCoin 141/141, nestest 0-diff, and every committed DMA oracle ROM — the five dmc_dma_during_read4 ROMs and both sprdma_and_dmc_dma ROMs — still Passed).
• Rp2A03H is a purely additive, opt-in knob that omits the double-halt extra read in the model. It is deterministic and reachable only when explicitly selected; the shipped/default build never touches it. On this engine the extra-read gate is a documented no-op on every committed oracle, so today Rp2A03H produces a byte-identical result to Rp2A03G across the entire committed DMA corpus (proven by the cpu_2a03_revision tests): the halted-DMC overlap-read fires but its parked address is always the post-$4014 instruction fetch, never a side-effect register (see below). The revision difference is therefore a mechanism-level model, not an observable divergence — ADR 0033.

The revision is a config knob re-applied on load, not part of the save-state (like the optional OAM-decay model): the only state it influences is fully re-derived from the deterministic timeline, so a save/restore round-trip stays byte-identical for a fixed revision. See docs/adr/0033-cpu-2a03-revision-dma-frontier.md.

Variants

Rp2A03G

RP2A03G — the common early/mid die the accuracy oracles were captured against. Performs the double-halt “unexpected DMA” extra read. This is the default and the byte-identical baseline.

Rp2A03H

RP2A03H — a later die modeled as omitting the double-halt extra read. Opt-in, additive, deterministic — but an unverified direction (no reference / no ROM proves it; see the type-level docs and ADR 0033).

Implementations

impl Cpu2A03Revision

pub const fn has_unexpected_dma_extra_read(self) -> bool

Whether this revision performs the “unexpected DMA” extra re-read of the parked address bus on the DMC-halt-coincides-with-OAM-halt overlap cycle. true for Rp2A03G (the default / byte-identical baseline), false for Rp2A03H.

Trait Implementations

impl Clone for Cpu2A03Revision

fn clone(&self) -> Cpu2A03Revision

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Cpu2A03Revision

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for Cpu2A03Revision

fn default() -> Cpu2A03Revision

Returns the “default value” for a type.

impl Hash for Cpu2A03Revision

fn hash<__H: Hasher>(&self, state: &mut __H)

Feeds this value into the given Hasher.

fn hash_slice<H>(data: &[Self], state: &mut H)

where H: Hasher, Self: Sized,

Feeds a slice of this type into the given Hasher.

impl PartialEq for Cpu2A03Revision

fn eq(&self, other: &Cpu2A03Revision) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Cpu2A03Revision

impl Eq for Cpu2A03Revision

impl StructuralPartialEq for Cpu2A03Revision