Struct Dmc 

pub struct Dmc {
    pub irq_enable: bool,
    pub loop_flag: bool,
    pub current_addr: u16,
    pub bytes_remaining: u16,
    pub dac: u8,
    pub irq_flag: bool,
    /* private fields */
}

DMC channel state.

Fields

irq_enable: bool

IRQ enable bit ($4010 bit 7).

loop_flag: bool

Loop bit ($4010 bit 6).

current_addr: u16

Current memory address.

bytes_remaining: u16

Bytes remaining to fetch.

dac: u8

7-bit DAC value (0..=127).

irq_flag: bool

Latched IRQ flag (cleared by writing $4015).

Implementations

impl Dmc

pub const fn new(region: Region) -> Self

Construct a new DMC channel.

pub fn write_ctrl(&mut self, value: u8)

$4010 write: IRQ enable + loop + rate index.

Note: the public NTSC/PAL rate tables are the period in CPU cycles per output bit. The DMC timer ticks at the APU clock (= half CPU rate), so the internal reload value is cpu_period / 2 - 1.

pub fn write_dac(&mut self, value: u8)

$4011 write: direct 7-bit DAC.

pub fn write_sample_addr(&mut self, value: u8)

$4012 write: sample address.

pub fn write_sample_length(&mut self, value: u8)

$4013 write: sample length.

pub const fn active(&self) -> bool

Status ($4015 read bit 4): bytes-remaining > 0.

pub fn set_enabled(&mut self, enabled: bool)

$4015 write effect on DMC: bit 4 set restarts sample if not running; bit 4 clear silences (sets bytes-remaining=0). Always clears irq_flag.

pub const fn needs_dma(&self) -> bool

Returns true if the DMC needs a DMA fetch right now (sample buffer empty and bytes remaining). Caller is responsible for halting the CPU and supplying the byte via Self::deliver_sample.

pub const fn dma_addr(&self) -> u16

The address the DMA controller must read.

pub fn deliver_sample(&mut self, byte: u8)

Consume a fetched byte from the DMA controller.

pub fn clock_timer(&mut self)

One APU clock — drives the timer, output unit, and (on buffer empty) loads the shift register from the sample buffer.

pub const fn output(&self) -> u8

Per-cycle output (0..=127).

pub const fn timer(&self) -> u16

Diagnostic: current byte-timer countdown value. Used by the per-cycle DMC-DMA cross-diff tracing (crates/rustynes-test-harness/src/bin/ trace_dma_4015.rs) to expose the internal byte-timer phase that the abort-context reload arm depends on.

pub const fn bits_remaining(&self) -> u8

Diagnostic: bits remaining in the output shift register (0..=8).

pub const fn silence(&self) -> bool

Diagnostic: output-unit silence flag.

pub const fn buffer_full(&self) -> bool

Diagnostic: sample buffer occupied (a byte awaits transfer to the shift register).

Trait Implementations

impl Clone for Dmc

fn clone(&self) -> Dmc

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Dmc

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Copy for Dmc