Module vu 

The vector unit — the RSP’s 8-lane SIMD coprocessor (Sprint 2).

32 registers of 128 bits, each eight lanes of 16 bits, exposed through COP2. This module currently implements the register file and the SU/VU moves; the computational instructions, the 48-bit accumulator and the VRCP/VRSQ tables are the rest of the sprint.

Lanes are a view over bytes, not the storage

Every move here addresses the register by byte offset, not by lane, and the two disagree in ways that matter: MTC2 with an odd offset straddles two lanes, and an offset of 15 wraps. Modeling the register as eight u16s and converting at the edges is what keeps that expressible — the alternative, treating a lane as the unit, silently rounds every odd offset.

Modules

rom

The VRCP / VRSQ reciprocal ROMs.

Structs

Control

The VU’s three control registers (N64brew RSP CPU Core §Control registers).

Divide

The reciprocal unit’s staging latches.