Struct Bus 

pub struct Bus {
    pub tia: Tia,
    pub riot: Riot,
    pub board: Option<Cartridge>,
    pub open_bus: u8,
    pub write_log: WriteLog,
}

The main system bus for Rusty2600, holding the chips.

Fields

tia: Tia

The TIA video/audio chip.

riot: Riot

The RIOT RAM/Timer/IO chip.

board: Option<Cartridge>

The cartridge board (mapper).

open_bus: u8

Open bus value (last driven value).

write_log: WriteLog

The debugger’s optional write log — see WriteLog.

Implementations

impl Bus

pub fn new() -> Self

pub fn peek(&self, addr: u16) -> u8

Side-effect-free read, for debugger/tooling use only: a real cpu_read can trigger bankswitch hotspots, RIOT’s INTIM read-clears-underflow-flag behavior, and cart snoop_read side effects, none of which a memory-viewer peek should ever cause. Reads via a full clone of self (cheap relative to a UI refresh cadence, and correctly avoids the unsafe-free crate’s inability to alias a &mut for a “no-op” read) so the real system state is untouched.

For more than a byte or two, prefer Self::peek_range — it clones self ONCE and reads every byte from that one clone, instead of paying a full Bus clone (TIA + RIOT + the cart’s ROM/RAM) per byte.

pub fn peek_range(&self, base: u16, len: u16) -> Vec<u8>

Side-effect-free read of len consecutive addresses starting at base (wrapping at 16 bits), for a debugger memory viewer or a disassembly window. Clones self once, then reads every byte from that single clone — any bankswitch hotspot triggered by reading byte N is visible to byte N+1’s read (an honest reflection of “whatever the bank state currently is,” same caveat any bank-switched-system memory viewer has), but the REAL system is never touched.

pub fn cpu_read(&mut self, addr: u16) -> u8

pub fn cpu_write(&mut self, addr: u16, val: u8)

Trait Implementations

impl AudioBus for Bus

fn audio_sample(&self) -> u8

impl Clone for Bus

fn clone(&self) -> Bus

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl CpuBus for Bus

fn read(&mut self, addr: u16) -> u8

fn write(&mut self, addr: u16, val: u8)

fn tick_cycle(&mut self)

Advance the rest of the system (TIA/RIOT/cart) by exactly one CPU cycle’s worth of real time. Called once per bus access the CPU makes, so a multi-cycle instruction advances the world cycle-by-cycle instead of all at once — this is what keeps the CPU’s notion of elapsed time in lockstep with the TIA’s color clock. Default no-op for buses that don’t model timing (flat-RAM test harnesses, the Klaus functional-test bus).

fn rdy_stall(&self) -> bool

Whether the bus is holding RDY low (the WSYNC beam-stall). The CPU spins on [Self::tick_cycle] while this is true instead of performing its next access. Default false for buses with no such concept.

impl Debug for Bus

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for Bus

fn default() -> Bus

Returns the “default value” for a type.

impl<'de> Deserialize<'de> for Bus

fn deserialize<__D>(__deserializer: __D) -> Result<Self, __D::Error>

where __D: Deserializer<'de>,

Deserialize this value from the given Serde deserializer.

impl Serialize for Bus

fn serialize<__S>(&self, __serializer: __S) -> Result<__S::Ok, __S::Error>

where __S: Serializer,

Serialize this value into the given Serde serializer.