Expand description
TPM MMIO base addresses and register offsets (platform-specific)
Constants§
- CRB_
BUFFER_ SIZE - Maximum command/response buffer size
- CRB_
CTRL_ CANCEL - CRB control cancel register
- CRB_
CTRL_ CMD_ HADDR - CRB command buffer address (high)
- CRB_
CTRL_ CMD_ LADDR - CRB command buffer address (low)
- CRB_
CTRL_ CMD_ SIZE - CRB command buffer size
- CRB_
CTRL_ REQ - CRB control request register
- CRB_
CTRL_ RSP_ ADDR - CRB response buffer address
- CRB_
CTRL_ RSP_ SIZE - CRB response buffer size
- CRB_
CTRL_ START - CRB control start register
- CRB_
CTRL_ STS - CRB control status register
- CRB_
DATA_ BUFFER - CRB data buffer (command/response share this region)
- CRB_
LOC_ CTRL - TPM CRB locality control
- CRB_
LOC_ STATE - TPM CRB locality 0 offset
- CRB_
LOC_ STS - TPM CRB locality status
- CRB_
START - Start command processing
- STS_
COMMAND_ READY - TPM is ready to accept a command
- STS_
DATA_ AVAIL - Data is available to read
- STS_
EXPECT - TPM expects more data
- STS_
VALID - TPM has completed processing
- TPM2_
BASE - Standard TPM 2.0 MMIO base address (x86_64)
- TPM_
ACCESS - TPM access register offset (FIFO interface)
- TPM_
DATA_ FIFO - TPM data FIFO offset (FIFO interface)
- TPM_
INTERFACE_ ID - TPM interface ID offset
- TPM_STS
- TPM status register offset (FIFO interface)