Module cache_topology 

Cache topology detection and cache-aware memory allocation

Detects CPU cache hierarchy (L1/L2/L3) using architecture-specific mechanisms:

• x86_64: CPUID leaf 4 (Intel) and leaf 0x8000001D (AMD)
• AArch64: hardcoded defaults (Cortex-A72)
• RISC-V: hardcoded defaults

Provides cache coloring support for NUMA-aware, cache-friendly page allocation.

Structs

CacheInfo

Information about a single cache level

CacheTopology

Complete cache topology for the current CPU

Enums

CacheLevel

Cache level

CacheType

Cache type classification

Functions

frame_color

Determine which cache color a physical frame belongs to.

get_cache_info

Access the global cache topology (read-only).

init

Initialize the cache topology subsystem.

is_initialized

Check if cache topology has been initialized

num_colors

Get the total number of cache colors available

preferred_color

Suggest a preferred cache color for a given process.