Expand description
MMIO register block offsets (per amdgpu driver documentation)
Constants§
- DCN_
BASE - Display Core Next engine base
- GFX_
RING_ BASE - GFX ring buffer base
- GRBM_
STATUS - Graphics Register Bus Manager status
- IH_
RB_ BASE - Interrupt handler ring buffer base
- MC_
HUB_ BASE - Memory controller hub base
- MMIO_
DATA - Memory-mapped register data
- MMIO_
INDEX - Memory-mapped register index/data pair
- SDMA0_
BASE - SDMA (System DMA) engine 0 base
- SMU_
BASE - Power management base
- SRBM_
STATUS - System Register Bus Manager status
- VCN_
BASE - Video Core Next decode engine base