rustysnes_cart/coproc/armv3/
bus.rs

1//! The host-facing memory surface the ARM core reads/writes through (mirrors the
2//! `Hg51bBus`/`rustysnes_cpu::Bus` pattern already used elsewhere in this codebase).
3
4/// A 24-bit-ish ARM-side address space accessor.
5///
6/// The concrete board wrapper (not yet built, `docs/st018-arm-notes.md` step 9) implements this
7/// over PRG ROM / data ROM / work RAM / the SNES-side handshake registers, and is also where the
8/// ARM's own cycle counter advances (every method call here corresponds to one real bus cycle on
9/// real hardware).
10pub trait ArmBus {
11    /// Fetch one instruction word (an aligned, sequential-or-not code read).
12    fn read_code(&mut self, addr: u32) -> u32;
13    /// Read a data word or byte (`LDR`/`SWP`/`LDM`). `byte` selects an 8-bit access.
14    fn read(&mut self, addr: u32, byte: bool) -> u32;
15    /// Write a data word or byte (`STR`/`SWP`/`STM`).
16    fn write(&mut self, addr: u32, value: u32, byte: bool);
17    /// One internal/idle bus cycle (register-specified shift amounts, multiply, `SWP`'s
18    /// between-read-and-write gap, etc. — real hardware spends a cycle here even though no
19    /// address is touched).
20    fn idle(&mut self);
21}
rustysnes_cart/coproc/armv3/bus.rs

rustysnes_cart/coproc/armv3/
bus.rs
