rustynes_core/scheduler.rs
1//! Lockstep-scheduler types shared across the bus, the IRQ-timing trace
2//! fixture, and (in Phase B+) the CPU IRQ sampling path.
3//!
4//! Currently re-exports [`M2Phase`] (canonical reference enum for "which
5//! half of the 6502 cycle the lockstep bus is currently in") from
6//! `rustynes-cpu`. The definition lives in `rustynes-cpu` because the
7//! [`rustynes_cpu::Bus`] trait method `poll_irq_at_phase` is parameterised
8//! over it; consumers of `rustynes-core` (the frontend, the test harness,
9//! the `irq_trace` fixture) continue to import the enum from
10//! `rustynes_core::scheduler` via this re-export so existing import paths
11//! stay unchanged.
12//!
13//! See `docs/scheduler.md` and `docs/adr/0002-irq-timing-coordination.md`
14//! for the surrounding design.
15
16pub use rustynes_cpu::M2Phase;