Constant APU_SNAPSHOT_VERSION 

pub const APU_SNAPSHOT_VERSION: u8 = 5;

Schema version for the APU snapshot blob.

• v1 (v0.9.0 .. v1.0.0-rc2): original schema with FrameCounter carrying a pending_irq_clear: bool consumed at the next tick.
• v2 (Session-25, 2026-05-23): FrameCounter replaces the bool with a irq_flag_clear_cycle: u64 lazy-clear schedule mirroring Mesen2’s _irqFlagClearClock. Old v1 blobs restore by migrating the bool to a synthesized schedule (a pending clear becomes “schedule for cpu_cycle + 1”, a fresh clear).
• v3 (Session-26 Sprint 2 iter 5, 2026-05-23 onwards): FrameCounter adds irq_line_active: bool as a SEPARATE field from irq_flag. v2 blobs migrate by setting both fields to the v2 irq_flag value (the IRQ-line state coincided with $4015 bit 6 visibility under the v2 conflated model). Per ADR-0003, the v2 -> v3 migration may show a 1-cycle transient where a reloaded inhibited state has the CPU IRQ line deasserted as the FC step re-establishes it — acceptable.
• v4 (2026-07-22): appends the scheduled warm-reset $4017 re-write (reset_4017_delay + reset_4017_value, 2 bytes). Apu::reset arms the countdown at 2 and tick_with_external decrements it once per CPU cycle, issuing FrameCounter::write when it hits zero (the v2.0.0 beta.3 A4 cycle-accurate reset, calibrated against blargg 4017_timing). Both fields were previously unserialized, so a snapshot taken inside that 2-cycle window restored delay = 0 and dropped the re-write entirely — the restored frame counter then kept the sequencer phase the re-write was supposed to reset. This is the same class as the PPU’s v5 / v6 / v8 tails (ADR 0030 / ADR 0034): live mid-frame state absent from the schema, invisible to any straight-run_frame test and reachable only through a snapshot/restore round trip. Surfaced by the standing schema audit (crates/rustynes-test-harness/tests/snapshot_schema_audit.rs) rather than by a user-visible symptom.

Since v2.9.8 (ADR 0042) only v4 is read, with every field required: the earlier versions’ migrations and the trailing-optional tails (the v1.x DMC-DMA scheduling bytes and the W3-Stage-4 block) are gone. The v4 layout itself is unchanged, so the number did not move.

v5 (v2.9.9, NL-12): the blip resampler’s synthesis state (ring head, warm-up flag, integrator, the 32 delta slots still in flight), so a save/load round trip at a frame boundary resumes the exact audio stream and serializes the same bytes as a run that never restored. v4 is refused (ADR 0042’s current-version-only rule).