Module pi 

The PI (Peripheral Interface) DMA engine + BSD domain timing registers. The PI (Peripheral Interface) DMA engine (T-14-001).

Moves bytes between RDRAM and the cartridge address space. Pulled forward from Phase 5 into Phase 1 because n64-systemtest loads the rest of its own ELF from cart through PI, so the Phase 1 exit criterion — and with it the v0.2.0 cut criterion — is unreachable without it.

Register map

From n64brew_wiki/markdown/Peripheral Interface.md:

Address	Register	Effect
0x0460_0000	PI_DRAM_ADDR	RDRAM side of the transfer
0x0460_0004	PI_CART_ADDR	cart side
0x0460_0008	PI_RD_LEN	write triggers RDRAM → cart
0x0460_000C	PI_WR_LEN	write triggers cart → RDRAM
0x0460_0010	PI_STATUS	read: busy flags; write: reset / clear IRQ

The two rules that bite

• Length is len + 1 bytes. Writing 0 transfers one byte, not zero. An implementation that transfers len is short by one on every single DMA, which corrupts the last byte of every block — a failure that looks like memory corruption rather than a DMA bug.
• RD and WR are named from the cartridge’s point of view, so PI_WR_LEN — the one everything actually uses — moves data cart → RDRAM. Getting them the wrong way round makes the first ROM load write the ROM’s own image over itself with uninitialized RDRAM.

Structs

Pi

The PI register file and DMA state.

Transfer

A transfer the PI has been asked to perform.

Constants

PI_BASE

Base of the PI register block.

PI_BSD_DOM1_LAT

PI_BSD_DOM1_LAT — domain-1 latency. DOM2’s block follows at +0x10.

PI_BSD_DOM1_PGS

PI_BSD_DOM1_PGS — domain-1 page size (2^(PGS+2) bytes).

PI_BSD_DOM1_PWD

PI_BSD_DOM1_PWD — domain-1 pulse width.

PI_BSD_DOM1_RLS

PI_BSD_DOM1_RLS — domain-1 release.

PI_BSD_DOM2_LAT

PI_BSD_DOM2_LAT — domain-2 latency (the SRAM / FlashRAM bus).

PI_BSD_DOM2_PGS

PI_BSD_DOM2_PGS — domain-2 page size.

PI_BSD_DOM2_PWD

PI_BSD_DOM2_PWD — domain-2 pulse width.

PI_BSD_DOM2_RLS

PI_BSD_DOM2_RLS — domain-2 release (end of the register block).

PI_CART_ADDR

PI_CART_ADDR.

PI_DRAM_ADDR

PI_DRAM_ADDR.

PI_RD_LEN

PI_RD_LEN — writing it starts an RDRAM → cart transfer.

PI_STATUS

PI_STATUS.

PI_WR_LEN

PI_WR_LEN — writing it starts a cart → RDRAM transfer.

STATUS_DMA_BUSY

PI_STATUS bit 0 — a DMA is in progress.

STATUS_INTERRUPT

PI_STATUS bit 3 — the PI interrupt is asserted.

STATUS_IO_BUSY

PI_STATUS bit 1 — an I/O transfer is in progress.

STATUS_W_CLR_INTR

PI_STATUS write bit 1 — clear the PI interrupt.

STATUS_W_RESET

PI_STATUS write bit 0 — reset the controller and abort any DMA.