rusty2600_core/lib.rs
1//! `rusty2600-core` — the Bus + the master-clock lockstep scheduler. The single
2//! crate that knows about every chip; it re-exports their public types so
3//! downstream consumers depend on `rusty2600-core`, not the chip crates
4//! directly.
5//!
6//! The timebase is integer TIA color clocks with the 6507 on every third one and
7//! the `WSYNC`/`RDY` beam-stall freezing the CPU — see [`scheduler`]. The Bus
8//! owns the TIA (video + audio), the RIOT (RAM + I/O + timer), and the cart
9//! board; there is no separate WRAM (the 2600's only RAM is in the RIOT) — see
10//! [`bus`].
11
12#![no_std]
13#![forbid(unsafe_code)]
14#![allow(warnings)]
15extern crate alloc;
16
17pub mod bus;
18pub mod movie;
19pub mod save_state;
20pub mod scheduler;
21
22// Re-export the chip crates (the public surface).
23pub use rusty2600_cart as cart;
24pub use rusty2600_cpu as cpu;
25pub use rusty2600_riot as riot;
26pub use rusty2600_tia as tia;
27
28pub use bus::{AudioBus, Bus, VideoBus, WriteEvent, WriteLog};
29pub use movie::{Movie, MovieError, MovieFrame, MovieRegion, MovieStart};
30pub use save_state::{SaveState, SaveStateError};
31pub use scheduler::System;
32
33// Re-export the cart tiering types so the test-harness honesty gate (and any
34// downstream consumer) reaches them through the core, not the chip crate.
35pub use rusty2600_cart::{Board, Tier, detect};